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w83194r - kx 133mhz 3 - dimm k7 clo ck publication release date: nov . 1999 - 1 - revision 0.3 5 1.0 general descrip tion the w83194r - kx is a clock generator which provides all clocks required for amd k7 system. w83194r - kx provides one differential pair cpu clock open drain outputs up to 143mhz which are externally selectable with smooth transitions . w83194r - kx also provides 6 pci clocks and 13 sdram clocks controlled by the none - delay buffer_in pin. the w83194r - kx accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. spread spectrum built in at 0.5% or 0.25% to reduce emi. programmable stopping individual clock outputs and frequency selection through i 2 c interface. the device meets the pentium power - up stabilization, which requires cpu and pci clocks be stable within 2 ms after power - up. high drive six pci and thirteen sdram clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. two cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads, when maintaining 50 5% duty cycle. the fixed frequency outputs, such as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2.0 product feature s supports amd k7 cpu with i 2 c. one pair of differential cpu clocks one chipset clock 13 sdram clocks for 3 dimms 6 pci synchronous clocks optional single or mixed supply: (vddq3=vddq2 =3. 3v) or (vddq3 = 3.3v, vddq2 = 2.5v) < 250ps skew among cpu clocks < 250ps skew among pci clocks < 5ns propagation delay sdram from buffer input skew from cpu(earlier) to pci clock 1.5 to 4ns, center 2.6ns. smooth frequency switch with selections from 66.8 mhz to 143 mhz cpu i 2 c 2 - wire serial interface and i 2 c read back 0.25% or 0.5% spread spectrum function to reduce emi programmable registers to enable/stop each output and select modes (mode as tri - state or normal ) one 48 mhz for usb & o ne 24 mhz for super i/o 48 - pin ssop package
w83194r - kx preliminary publication release date: nov . 1999 - 2 - revision 0.35 3.0 block diagram pll2 xtal osc spread spectrum pll1 latch por 1/2 config. reg. stop pci clock divider ~ ~ 4 13 6 48mhz 24_48mhz ref0/cpu_stop# cput0 sdram(0:12) pciclk(0:5) xin xout buffer in fs(0:3)* 4 mode* sdata* sdclk* cpuc0 cput_cs pd# ~ ref1 4.0 pin configurati on
w83194r - kx preliminary publication release date: nov . 1999 - 3 - revision 0.35 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddq3 cpu_stop#/ref0 vss xin xout vddq3 pciclk0/mode* pciclk1/fs1* vss pciclk2 pciclk3 pciclk4 pciclk5 vddq3 buffer in vss sdram11 sdram10 vddq3 sdram 9 sdram 8 vss sdata* sdclk* ref1/fs0* vss cput_cs cpuc0 vddq2 pd# sdram12 vss sdram 0 sdram 1 sdram 2 vddq3 sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vddq3 vddq3 48mhz/fs2* 24_48mhz/fs3* cput0 vss 5.0 pin description in - input out - output i/o - bi - directional pin # - active low * - internal 250k w pull - up 5.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and feedback resistors. xout 5 out crystal output at 14.318mhz nominally. 5.2 cpu, sdram, pci, ioapic clock outputs symbol pin i/o function cput_cs cpu_c0 cpu_t0 46 4 4 43 od cpu_c0 and cpu_t0 are the differential open drain cpu clocks for k7. cput_cs is the open drain pin for the chipset. it has the same phase relationship as cpu_t0.
w83194r - kx preliminary publication release date: nov . 1999 - 4 - revision 0.35 sdram [ 0:12] 17,18,20,21,28,2 9,31,32,34, 35,37,38,40 out sdram clock outputs. fanout buffer outputs from buffer in pin.(controlled by chipset) they are disabled when pd# is set low. pciclk0/ *mode 7 i/o free running pci clock during normal operation. latched input. mode=1, pin 2 is ref0; mode=0, pin2 is cpu_stop# pciclk1/*fs1 8 i/o low skew (< 250ps) pci clock outputs. latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. pciclk [ 2:5 ] 10,11,12,13 out low skew (< 250ps) pci clock outputs. synchronous to cpu clocks with 1 - 48ns skew(cpu early). buffer in 15 in inputs to fanout for sdram outputs. pd# 41 in the all clocks will be stopped when this pin set to low .
w83194r - kx preliminary publication release date: nov . 1999 - 5 - revision 0.35 5.3 i 2 c control interface symbol pin i/o function *sdata 23 i/o serial data of i 2 c 2 - wire control interface with internal pull - up resistor. *sdclk 24 in serial clock of i 2 c 2 - wire control interface with internal pull - up resistor. 5.4 fixed frequency outputs symbol pin i/o function ref0 / cpu_stop# 2 i/o 14.318mhz reference clock. this ref output is the stronger buffer for isa bus loads. halt cpu clocks at logic 0 level, when input low (in mobile mode. mode=0) ref1 / *fs0 48 i/o 14.318mhz reference clock. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdra m and pci clocks. 24_48mhz / *fs3 25 i/o 24mhz output clock. latched input for fs3 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48mhz / *fs2 26 i/o 48mhz output for usb during normal operation. latched input for fs2 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 5.5 power pins symbol pin function vddq2 42 power supply for cpu clocks, 2.5v or 3.3v. vddq3 1,6,14,19,27,30,36 power supply for pci, 24_48mhz, sdram[0:12] , and cpu pll core, nominal 3.3v. vss 3,9,16,22,33,39,45, 47 circuit ground.
w83194r - kx preliminary publication release date: nov . 1999 - 6 - revision 0.35 6.0 frequency selec tion 6.1 h/w setting frequency table fs3 fs2 fs1 fs0 cpu(mhz) pci(mhz) 1 1 1 1 95 31.7 1 1 1 0 103 34.3 1 1 0 1 105 35 1 1 0 0 108 36 1 0 1 1 90 30 1 0 1 0 110 36.7 1 0 0 1 115 38.3 1 0 0 0 120 30 0 1 1 1 133.3 33.3 0 1 1 0 83 33.3 0 1 0 1 100.2 33.3 0 1 0 0 66.8 33.4 0 0 1 1 124 31 0 0 1 0 129 32.3 0 0 0 1 138 34.5 0 0 0 0 143 35.8 7.0 mode pin - power management input co ntrol mode, pi n7 (latched input) pin 2 0 cpu_stop# (input) 1 ref0 (output)
w83194r - kx preliminary publication release date: nov . 1999 - 7 - revision 0.35 8.0 funtion descrip tion 8.1 power management functions all clocks can be individually enabled or disabled via the 2 - wire control interface. on power up, external circuitry should allow 3 ms for the vco to stabilize prior to enabling clock outputs to assure correct pulse widths. when mode=0, pins 2 is inputs (cpu_stop#), when mode=1, these functions are not available. the w83194r - kx may be disabled in the low state according to the pd# pin 41 in order to reduce power consumption. all clocks are stopped in the power down state when pd# is set to low, but maintain a valid high period on transitions from running to stop. 8.2 2 - wire i 2 c control interface the clock generator is a slave i 2 c component which can be read back the data stored in the latches for verification. all proceeding bytes must be sent to change one of the control bytes. the 2 - wire control interface allows each clock output individually enabled or disabled. on power up, the w83194r - kx initializes with default register settings. use of the 2 - wire control interface is then optional. the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high during normal data transfer. there are only two exceptions. one is a high - to - low transition on sdata while sdclk is high used to indicate the beginning of a data transfer cycle. the other is a low - to - high transition on sdata while sdclk is high used to indicate the end of a data transfer cycle. da ta is always sent as complete 8 - bit bytes followed by an acknowledge generated. byte writing starts with a ? start ? condition followed by 7 - bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. after successful reception of each byte, an ? acknowledge ? (low) on the sdata wire will be generated by the clock chip. controller can start to write to internal i 2 c registers after the string of data. the sequence order is as follows: bytes sequence ord er for i 2 c controller : clock address a(6:0) & r/w ack 8 bits dummy command code ack 8 bits dummy byte count ack byte0,1,2... until stop set r/w to 1 when ? read back ? , the data sequence is as follows, address is [1101 0011] : clock address a(6:0) & r/w ack byte 0 ack ack byte2, 3, 4... until stop byte 1
w83194r - kx preliminary publication release date: nov . 1999 - 8 - revision 0.35 8.3 serial control registers the pin column lists the affected pin number and the @powerup column gives the default state at true power up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the sequence described below (register 0, register 1, register 2, ....) will be valid and acknowledged. frequency table by software via i2c ssel3 ssel2 ssel1 ssel0 cpu(mhz) pci(mhz) 1 1 1 1 95 31.7 1 1 1 0 103 34.3 1 1 0 1 105 35 1 1 0 0 108 36 1 0 1 1 90 30 1 0 1 0 110 36.7 1 0 0 1 115 38.3 1 0 0 0 120 30 0 1 1 1 133.3 33.3 0 1 1 0 83 33.3 0 1 0 1 100.2 33.3 0 1 0 0 66.8 33.4 0 0 1 1 124 31 0 0 1 0 129 32.3 0 0 0 1 138 34.5 0 0 0 0 143 35.8
w83194r - kx preliminary publication release date: nov . 1999 - 9 - revision 0.35 8.3.1 register 0: frequency select register (default = 0) bit @powerup pin description 7 0 - reserved 6 0 - ssel2 (for frequency table selection by software via i 2 c) 5 0 - ssel1 (for frequency table selection by software via i 2 c) 4 0 - ssel0 (for frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 6:4, bit2 2 0 - ssel3 (for frequency table selection by software via i 2 c) 1 0 - reserved 0 0 - reserved 8.3.2 register 1 : cpu clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 0 - reserved 6 0 - reserved 5 0 - reserved 4 0 - reserved 3 1 40 sdram12 (active / inactive) 2 0 - reserved 1 1 43 44 cput0 cpuc0 (active / inactive) 1 46 cput_cs (active / inactive) 8.3.3 register 2: pci clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 1 - reserved 6 1 7 pciclk0 (active / inactive) 5 1 - reserved 4 1 13 pciclk5 (active / inactive) 3 1 12 pciclk4 (active / inactive) 2 1 11 pciclk3 (act ive / inactive) 1 1 10 pciclk2(active / inactive) 0 1 8 pciclk1 (active / inactive)
w83194r - kx preliminary publication release date: nov . 1999 - 10 - revision 0.35 8.3.4 register 3: sdram, 24mhz, 48mhz clock register ( 1 = enable, 0 = stopped ) bit @powerup pin description 7 0 - reserved 6 0 - sel24_48 (select 24mhz or 48mhz for pin25) 5 1 26 48mhz (active / inactive) 4 1 25 24_48mhz (active / inactive) 3 0 - reserved 2 1 21,20,18, 17 sdram(8:11) (active / inactive) 1 1 32,31,29, 28 sdram(4:7) (active / inactive) 0 1 38,37,35, 34 sdram(0:3) (active / inactive) 8.3.5 registe r 4: reserved register (1 = enable, 0 = stopped) bit @powerup pin description 7 x - latched fs3# 6 x - latched fs2# 5 x - latched fs1# 4 x - latched fs0# 3 0 - reserved 2 0 - reserved 1 0 - 0 = 0.75% spread spectrum modulation 1 = 0.5% spread spectrum modulation 0 0 - 0 = normal 1 = spread spectrum enabled 8.3.6 register 5: peripheral control (1 = enable, 0 = stopped) bit @powerup pin description 7 0 - reserved 6 0 - reserved 5 0 - reserved 4 0 - reserved 3 0 - reserved 2 0 - reserved 1 1 46 ref1 (active / inactive) 0 1 2 ref0 (active / inactive)
w83194r - kx preliminary publication release date: nov . 1999 - 11 - revision 0.35 8.2.7 register 6: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 0 - winbond chip id 2 1 - winbond chip id 1 1 - winbond chip id 0 1 - winbond chip id
w83194r - kx preliminary publication release date: nov . 1999 - 12 - revision 0.35 13.0 ordering infor mation part number package type production flow w83194r - kx 48 pin ssop commercial, 0 c to +70 c 14.0 how to read th e top marking 1st line: winbond logo and the type number: w83194r - kx 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 814 g a b 814 : packages made in ' 98 , week 14 g : assembly house id; a means ase, s means spil, g means gr a : internal use id b : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83194r - kx 28051234 814gab
w83194r - kx preliminary publication release date: nov . 1999 - 13 - revision 0.35 15.0 package drawin g and dimensions headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in s uch applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.

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